Data reliability is extremely important to the performance of a system in the field of error tolerant computer. Data is stored in a Dynamic Random Access Memory (“DRAM”) in the runtime of the system. Due to liability to error during data storage in the DRAM, error detection and correction on the memory is a very important type of reliability technology in the field of error tolerant computer.
Nowadays, a cache in an Intel processor has a row size of 64 Byte or 128 Byte. For a Dual In-line Memory Module (“DIMM”) with Error Correction Code (“ECC”), correction to content failure in a DRAM granularity is realized by means of 32-byte data plus a 32-bit ECC in the current error correction scheme. In a DIMM consisting of x4 DRAM granularities, data arrangement of 32-byte data plus a 32-bit ECC check word in the DIMM is illustrated in FIG. 1, in which the dotted lines represent the omitted DRAM granularities, also referred to as Device, and the data therein. As illustrated in FIG. 1, data is stored in the DRAM granularities Device0-15, and ECC is stored in the DRAM granularities Device16-17. If a DRAM granularity, Device4, fails, error happens over 16 bits in an ECC word. Upon detection of the error, the ECC is operable to correct the error over the 16 bits and the corrected data is written back to the memory.
In the above-stated prior art, an ECC word is simply capable of detecting an error associated with two failed DRAM granularities, that is, a 32-bit error corresponding to two failed DRAM granularities. There is a problem as to insufficient capability of error detection.